Embodiments of the inventive concepts disclosed herein relate to interface circuits and, more particularly, to interface circuits configured to interface with multi-rank memory.
Semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. Read and write speeds of volatile semiconductor memory devices may be fast, but data stored therein may disappear when a power supply voltage is interrupted. In contrast, even if the power supply voltage is interrupted, nonvolatile semiconductor memory devices may retain data stored therein. In particular, volatile memory devices such as a dynamic random access memory (DRAM) may have fast read and write speeds. Accordingly, DRAM or DRAM modules may be used as a data storage device, such as a solid state drive (SSD), or as main memory of a computing system.
As demand for a high-capacity memory increases, the use of multi-rank memory devices may increase. In multi-rank memory, however, since dies arranged for respective ranks may be different from each other, it may be difficult to calibrate skew of data read from multi-rank memory. One issue, in which the size of a valid window of the read data is reduced, may occur even when the skew of data read from the multi-rank memory may be adjustable. This may also cause a serious problem, such as a read fail. In addition, the high capacity of the multi-rank memory may cause an increase in the throughput of the interface circuit that performs interfacing with the multi-rank memory. Therefore, power consumption of the interface circuit may increase.